IP Design Director

We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. 

Key Responsibilities: 

• Design and implement high-performance digital solutions, including RTL development and synthesis. 

• Collaborate with cross-functional teams on IP integration for processor IPs and peripherals 

• Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind 

• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. 

• Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. 

• Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows 

Basic Qualifications / Experience Level: 

• Bachelor’s in Electronics/Electrical engineering (Master's preferred). 

• Minimum 15+ years of digital design experience, with focus on processor, peripherals and full chip implementation. 

• Proven expertise in RTL development, synthesis, and timing closure. 

• Experience with front-end design, gate-level simulations, and design verification. 

• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. 

Required Expertise: 

• Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes (< 16nm) 

• Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles .

• Hands-on experience with processor IP (ARM/ARC) 

• Experience of working on PCIe is a must. 

• Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART 

• Hands-on experience with complex DMA engines and FW interaction.

• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). 

• Experience with block-level and full-chip design at advanced nodes (≤ 16nm). 

• Silicon bring-up and po