Hiring: Staff Engineer - STA
Location: Hyderabad / Bangalore
Experience: 10+ Years
Notice Period: Immediate to 30 Days Preferred
Role Overview
We are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in timing sign-off for complex SoC designs. The candidate should have hands-on experience in timing closure, constraints development, and working closely with PD and RTL teams to achieve design closure.
Key Responsibilities
- Perform block and full-chip Static Timing Analysis for complex SoC designs
- Develop and validate timing constraints (SDC)
- Drive timing closure across different corners and modes
- Analyze and debug setup/hold violations
- Work closely with Physical Design, RTL, and Architecture teams
- Support ECO implementation for timing fixes
- Handle timing sign-off for tape-out
- Perform clock tree and timing path analysis
Mandatory Skills
- Strong expertise in Static Timing Analysis (STA)
- Hands-on experience with Synopsys PrimeTime
- Strong understanding of timing constraints (SDC)
- Experience in timing closure and sign-off
- Understanding of clocking architecture and CDC concepts
- Exposure to advanced technology nodes
- Good understanding of Physical Design flow
Good to Have
- Experience with CPU/GPU or high-performance SoC designs
- Knowledge of Low Power (UPF/CPF)
- Exposure to Synthesis and PD flow
- Experience in ECO and sign-off flows
Required Experience
- 10+ years of experience in STA / Timing Analysis
- Strong debugging and problem-solving skills
- Ability to work independently and drive timing closure
Interested candidates can share resumes with [HIDDEN TEXT]