DV with DRAM Memory controller/ NOC

2

Required Technical Skill Set**

DV with DRAM Memory controller/ NOC

3

Desired Experience Range**

5years

4

Location of Requirement

Hyderabad

Must-Have** (not more than 3-5)

•    System Verilog based UVM Functional verification, Behavioral modelling of functional blocks.

•    System level performance verification, traffic patterns, bandwidth & latency analysis.

•    Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol.

•    Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.

•    Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.